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VLSI projects - Empyreal Solution
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VLSI projects

2014-2015 VLSI Projects

S.No Project Titles
001 Low-Power and Area-Efficient Carry Select Adder
002 Design of Dedicated Reversible Quantum Circuitry for Square Computation
003 Razor Based Programmable Truncated Multiply and Accumulate, Energy-Reduction for Efficient Digital Signal Processing
004 A Decimal/Binary Multi-operand Adder Using a Fast Binary to Decimal Converter
005 All Optical Reversible Multiplexer Design using Mach-Zehnder Interferometer
006 Memory Footprint Reduction for Power-Efficient Realization of 2-D Finite Impulse Response Filters
007 Designing Hardware-Efficient Fixed-Point FIR Filters in an Expanding Subexpression Space
008 Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low Adaptation-Delay
009 Low – Power Digital signal Processor Architecture for wireless sensor Nodes
010 Time-Based All-Digital Technique for Analog Built-in Self-Test
011 Analysis and Design of a Low – voltage Low – Power Double Tail Comparator
012 A new hydrid  multiplier using Dadda and Wallace method
013 Parallel multiplier – accumulator based on radix- 2 modified Booth algorithm by using a VLSI architecture
014 Fully Reused VLSI Architecture of FM0 / Manchester encodingUsing SOLS Technique for DSRC Applications
015 Reverse Converter Design Via Parallel – Prefix Adders: Novel Components, Methodlogy , and Implementations
016 Bit – Level Optimization of Adder – Trees for Multiple Constant Multiplications for Efficient FIR Filter Implementation
017 Implementation of floating point MAC Using Residue Number System
018 4-2 Compressor Design with New XOR-XNOR Module
019 Realization of 2:4 reversible decoder and its application
020 Novel Field _Programmable Gate Array Architecture for Computing the  Eigen Value  Decomposition of  Para – Hermitian Polynomial Matrices
021 Data Encoding Techniques for Reducing Energy Consumption  in Network _on _chip
022 Low-Complexity Low-Latency Architecture for Matching of Data Encoded with Hard Systematic Error – Correcting Codes
023 A Synergetic Use of  Bloom Filters For Error Detection and Correction
024 HIGH SPEED VEDIC MULTIPLIER DESIGNSA REVIEW
025 High- Throughput Multi Standard Transform Core Supporting MPEG/H.264/VC-1 Using Common Sharing Distributed Arithmetic
026 Quaternary Logic Lookup  Table in Standard CMOS
027 Universal Set of CMOS Gates for the Synthesis of  Multiple Valued Logic Digital Circuits
028 Fast Sign Detection Algorithm for the RNS Moduli Set {2n+1-1, 2n-1, 2n }
029 Hardware Efficient Mixed Radix-25/16/9 FFT for LTE Systems
030 VLSI Architecture Design of Guided Filter for 30 Frames/s Full-HD Video
031 Novel Reconfigurable Hardware Architecture for Polynomial Matrix Multiplications
032 A 16-Core Processor With Shared-Memory and Message-Passing Communications
033 32 Bit X 32 Bit  Multiprecision Razor- Based Dynamic Voltage Scaling Multiplier with Operands Scheduler
034 Multifunction Residue Architectures for Cryptography
035 Improved 8 –Point Approximate DCT for Image and Video Compression Requiring Only 14 Additions
036 Reliable Concurrent Error Detection Architectures for Extended Euclidean –Based Division Over $(rm GF} (2 ^{m})$
037 Reconfigurable CORDIC – Based Low – Power DCT Architecture Based on Data Priority
038 Area – Delay Efficient Binary  Adder in QCA
039 Low- Complexity Reconfigurable Fast Filter Bank  for Multi –Standard Wireless Recivers
040 Binary Division algorithm and high Speed Deconvolution algorithm (Based on Ancient Indian Vedic Mathematics)
041 Design and Implementation of Modified Signed – Digit  Adder
042 A Combined SDC-SDF Architecture for Normal I/O Pipelined Radix -2 FFT
043 Radix-2r Arithmetic for Multiplication by a Constant
044 Design of a Low-Voltage Low –DropOut Regulator
045 Design and Analysis of Approximate Compressors for Multiplication
046 Reviewing High –Radix Signed  – Digit Adders
047 Area – Delay – Power Efficient Carry –Select Adder
048 Method for designing Multi-Channel RNS Architectures to prevent  Power Analysis SCA
049 An Optimized Modified Booth Recoder for Efficient Design of the  Add- Multiply Operator
050 Energy Efficient Programmable MIMO Decoder Accelerator Chip in 65-nm CMOS
051 Precise VLSI Architecture for AI – Based 1-D/2-D Daub -6 Wavelet Filter Bank with Low Adder – Count
052 A Method to Extend Orthogonal Latin Square Codes
053 Low – Power Programmable PRPG With Test Compression Capabilities
054 Efficient FPGA and ASIC Realizations of a DA-Based Reconfigurable FIR Digital Filter
055 Novel Square root algorithm and its FPGA Implementation
056 High – Throughput Turbo Decoder with Parallel Architecture for LTE Wireless Communication Standards
057 Fast Radix -10 Multiplication Using Redunant BCD
058 A parallel radix –sort –based VLSI architecture for finding the first W maximum/minimum values
059 Performance Analysis of the  CS-DCSK /BPSK Communication System
060 VLSI Design of a Large – Number  Multiplier for  Fully – Homorphic Encryption

IEEE 2013  & 2012 Projects

S.No Project Titles
061 High-Speed Low-Power Viterbi Decoder Design for TCM Decoders
062 Efficient Majority Logic Fault Detection With Difference-Set Codes for Memory Applications
063 Soft-Error-Resilient FPGAs Using Built-In 2-D Hamming Product Code
064 Error Detection in Majority Logic Decoding of Euclidean Geometry Low Density Parity Check (EG-LDPC) Codes
065 Multi operand Redundant Adders on FPGAs
066 Data Encoding Schemes in Networks on Chip
067 A New VLSI Architecture of Parallel Multiplier–Accumulator Based on Radix-2 Modified Booth Algorithm
068 Design and Implementation of Multi-mode QC-LDPC Decode
069 Data Encoding for Low-Power in Wormhole-Switched Networks-on- Chip
070 Low Complexity Digit Serial Systolic Montgomery Multipliers For Special Class Of GF(2M)
071 Split-path Fused Floating Point Multiply Accumulate (FPMAC).
072 Design of Digit-Serial FIR Filters: Algorithms, Architectures, and a CAD Tool.
073 Low Power and Design Reed –Solomon Encoder
074 A Spurious-Power Suppression Technique for Multimedia/DSP Applications (MAC)
075 Digital Filter Implementation Based on the RNS with Diminished-1 Encoded Channel
076 Low Power 64bit Multiplier Design by Vedic Mathematics
077 VLSI implementation of Fast Addition using Quaternary Signed Digit Number System
078 An Efficient High Speed Wallace Tree Multiplier
079 Low Latency Systolic Montgomery Multiplier for finite Field GF (2m) Based on Pentanomials
080 Radix-4 and radix-8 booth encoded multi-modulus multipliers
081 Viterbi Based Efficient Test Data Compression
082 CORDIC Designs for Fixed Angle of Rotation
083 Product codes of MLC NAND  Flash  Memories
084 Pipelined Parallel FFT Architectures via Folding Transformation
085 High Speed Parallel Decimal Multiplication with Redundant Internal Encodings
086 Scalable Digital CMOS Comparator Using a Parallel Prefix Tree
087 Design and Implementation of High-Speed and Energy-Efficient Variable-Latency Speculating Booth Multiplier (VLSBM).
088 New High-Speed Multioutput Carry Look-Ahead Adders
089 Modulo 2n-2 Arithmetic Units
090 A New RNS based DA Approach fo Inner Product Computation
091 FPGA Architecture for OFDM Software Defined Radio with an optimized Direct Digital Frequency Synthesizer
092 Design and Implementation of 32 Bit Unsigned Multiplier Using CLAA and CSLA
093 Energy-Efficient High-Throughput Montgomery Modular Multipliers for RSA Cryptosystems
094 A Single-Channel Architecture for Algebraic Integer Based 8 x 8 2-D DCT Computation
095 Low Power and Design Reed –Solomon Encoder
096 Design Of An On – Chip Permutation  Network For Multiprocessor Soc
097 A Practical NoC Design for Parallel DES Computation
098 Low-Power Logarithmic Number System Addition/Subtraction and their Impact on  Digital Filters
099 Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through Scheme
100 Constant Delay Logic
101 Parallel AES Encryption Engines for Many- Core Processor Arrays.
102 Toeplitz Matrix Approach for Binary Field Multiplication Using Quadrinomials
103 VLSI Architecture of Arithmetic code used in SPHIT

 

  • Pragmatic Integration of SRAM Row Cache in Heterogeneous 3-D DRAM Architecture Using TSV
  • Built-in Self-Test Technique for Diagnosis of Delay Faults in Cluster-Based Field Programmable Gate Arrays
  • ASIC Design of Complex Multiplier
  • A Low Cost VLSI Implementation for Efficient Removal of Impulse Noise
  • FPGA Based Space Vector PWM Control IC For Three Phase Induction Motor Drive
  • VLSI Implementation of Auto Correlator and CORDIC Algorithm for OFDM Based WLAN
  • Automatic Road Extraction Using High Resolution Satellite Images
  • VHDL Design for Image Segmentation Using Gabor Filter for Disease Detection
  • A Low Complexity Turbo Decoder Architecture for Energy Efficient Wireless Sensor Networks
  • Improvement of The Orthogonal Code Convolution Capabilities Using FPGA Implementation
  • Design and Implementation of Floating Point ALU
  • CORDIC Design for Fixed Angle of Rotation
  • Product Reed-Solomon Codes for Implementing NAND Flash Controller on FPGA Chip
  • Statistical SRAM Read Access Yield Improvement Using Negative Capacitance Circuits
  • Power Management of MIMO Network Interfaces on Mobile Systems
  • Design of Data Encryption Standard for Data Encryption
  • Low Power and Area Efficient Carry Select Adder
  • Synthesis and Implementation of UART Using VHDL Codes
  • Improved Architectures for a Fused Floating-Point Add-Subtract Unit
  • An FPGA Based 1-Bit All Digital Transmitter Employing Delta-Sigma Modulation with RF Output for SDR
  • Optimizing Chain Search Usage in The BCH Decoder for High Error Rate Transmission
  • Digital Design of DS-CDMA Transmitter Using Verilog HDL and FPGA
  • Design and Implementation of Efficient Systolic Array Architecture
  • A VLSI-Based Robot Dynamics Learning Algorithm
  • A Versatile Multimedia Functional Unit Design Using the Spurious Power Suppression Technique
  • Design of Bus Bridge between AHB and OCP
  • Behavioral Synthesis of Asynchronous Circuits
  • Speed Optimization of a FPGA Based Modified Viterbi Decoder
  • Implementation of I2C Interface
  • A High-Speed/Low-Power Multiplier Using an Advanced Spurious Power Suppression Technique
  • Clamping Virtual Supply Voltage of Power Gated Circuits for Active Leakage Reduction and Gate Oxide Reliability
  • FPGA Based Power Efficient Channelizer for Software Defined Radio
  • VLSI Architecture and FPGA Prototyping of a Digital Camera for Image Security and Authentication
  • Operation Improvement of Indoor Robot
  • Design and Implementation of an ON-Chip Permutation Network for Multiprocessor System On-Chip
  • A Symbol-Rate Timing Synchronization Method for Low Power Wireless OFDM Systems
  • DMA Controller (Direct Memory Access ) Using VHDL/VLSI
  • Reconfigurable FFT Using CORDIC Based Architecture for MIMI-OFDM Receivers
  • Spurious Power Suppression Technique for Multimedia/DSP Applications
  • Efficiency of BCH Codes in Digital Image Watermarking
  • Dual Data Rate SD RAM Controller
  • Implementing Gabor Filter for Fingerprint Recognition Using Verilog HDL
  • Design of a Practical Nanometer Scale Redundant via Aware Standard Cell Library for Improved Redundant via 1 Insertion Rate
  • A Lossless Data Compression and Decompression Algorithm and Its Hardware Architecture
  • A Framework for Correction of Multi-Bit Soft Errors
  • Viterbi-Based Efficient Test Data Compression
  • Implementation of FFT/IFFT Blocks for OFDM
  • Wavelet Based Image Compression by VLSI Progressive Coding
  • VLSI Implementation of Fully Pipelined Multiplier Less 2d DCT/IDCT Architecture for Jpeg